The invention relates to a nonvolatile semiconductor memory cell and to a method for fabricating the memory cell.
Erasable read-only memories, xe2x80x9cFlash EPROMsxe2x80x9d (Erasable Programmable Read-Only Memories) and EEPROMs (Electrically Erasable Programmable Read-Only Memories) are known and are used as nonvolatile memory elements in a wide variety of areas of technology. Flash EPROMs and EEPROMs include a multiplicity of nonvolatile semiconductor memory cells which each include one or two transistors. The nonvolatile semiconductor memory cell is programmed by reversing the electrical charge on a floating gate, which can be carried out in various ways, depending on the design of the memory cell. The charge state of the floating gate which results from the charge reversal is conserved for a long time (a number of years).
Many applications require erasable read-only memories with short programming times and with long charge retention times. In addition, memory cells with two transistors have the drawback that they take up a relatively large amount of space.
Published European Patent Application EP 0 843 361 A1 discloses a memory component with a storage node that is arranged above a channel region of a transistor. A single layer stack having a square horizontal cross section and serving as a tunnel barrier structure is arranged over the storage node. The barrier structure, referred to as a xe2x80x9cmultiple tunnel junctionxe2x80x9d, has an alternating insulating layer and a conduction layer, the respective extent of which covers the entire channel region of a transistor. Alternatively, the conduction layer may be formed such that it has small conduction islands. A control electrode in the form of a word line is arranged on the layer stack. Charge is injected into the layer stack via the control electrode.
Another memory component in which a similar layer stack is formed over a channel region of a transistor and which likewise serves as a tunnel barrier layer is known from U.S. patent application Ser. No. 5,714,766.
The publication by H. Mizuta et al.: xe2x80x9cHigh-speed single-electron memory: cell design and architecturexe2x80x9d IEEE Comput. Soc., 12th-13th, March 1998, pp. 67-72, XP002151823 Los Alamitos/USA discloses a RAM memory component in which a stack structure used as a barrier system is formed above a storage node. The storage node is formed horizontally between a drain and a source region of a transistor. A word line is arranged on the stack structure, and via the word line, charges are injected into the layer stack which tunnel through the layer stack. In addition, the stack is surrounded by a trimming gate electrode that can be used to influence the tunneling of the charge carriers.
The publication xe2x80x9cPLEDxe2x80x94Planar Localized Electron Devicesxe2x80x9d by K. Nakazato, et al., IEDM 97-179, (1997) describes a semiconductor memory cell in which the floating gate electrode of an MOS (Metal Oxide Semiconductor) transistor is connected to a data line via a layer stack including alternate polysilicon and silicon nitride layers. The layer stack is bordered by a control gate electrode that can be used to alter the electrical potential in the peripheral area of the layer stack. Both the floating gate electrode and the control gate electrode are connected to a word line. By suitably driving the word line, the floating gate electrode can be connected to the data line and the charge on the floating gate electrode can be reversed. On the other hand, the insulating barriers (silicon nitride layers) of the layer stack result in a relatively long retention time for the charge if the gate voltage is not in line with the write or programming mode.
Published German Patent Application DE 196 32 835 A1 describes a semiconductor capacitor that has a capacitor electrode with a multiplicity of column structures to increase the size of the capacitor surface. The column structures are formed using a random mask that permits structure sizes in the sub-100 nm range.
Fit is accordingly an object of the invention to provide a nonvolatile semiconductor memory cell and a method for producing the memory cell which overcome the above-mentioned disadvantages Of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a nonvolatile semiconductor memory cell that is suitable for constructing large-scale integrated semiconductor memories and that also has a high ratio of storage time to programming time.
With the foregoing and other objects in view there is provided, in accordance with the invention, a nonvolatile semiconductor memory cell that includes: a substrate; a transistor component formed on the substrate; a control gate electrode; and a storage node that determines the switching state of the transistor component. The storage node is located near the control gate electrode. The storage node includes a group of a plurality of vertically oriented column structures. Each one of the vertically oriented column structures has at least two semiconductor layer zones and an insulating layer zone that is configured between the two semiconductor layer zones.
In accordance with an added feature of the invention, the transistor component includes a channel region; and the plurality of the vertically oriented column structures are randomly distributed above the channel region.
In accordance with an additional feature of the invention, a plurality of insulating layer zones are provided; the at least two semiconductor layer zones define a plurality of semiconductor layer zones. The insulating layer zone forms one of the plurality of the insulating layer zones; and the plurality of semiconductor layer zones and the plurality of the insulating layer zones are alternately configured.
In accordance with another feature of the invention, the control gate electrode at least partly surrounds each one of the plurality of the vertically oriented column structures of the storage node.
In accordance with a further feature of the invention, the transistor component has a floating gate electrode; and the storage node is capacitively coupled to the floating gate electrode.
In accordance with a further added feature of the invention, the transistor component has a floating gate electrode; and the storage node coupled to the floating gate electrode by an electrically conductive connection.
In accordance with a further additional feature of the invention, the storage node forms a gate electrode of the transistor component.
In accordance with yet an added feature of the invention, each one of the plurality of the vertically oriented column structures has a diameter of less than 50 nm, and preferably of less than 30 nm.
In accordance with yet another feature of the invention, the two semiconductor layer zones have an axial thickness of less than 10 nm, and preferably of less than 3 nm.
By using a plurality of column structures having at least one respective insulating layer zone acting as a charge barrier at the storage node, it is possible to obtain a semiconductor memory cell that has a long storage time. The storage time corresponds to a characteristic time during which charge (in the read mode) flows away from the storage node, i.e. in which the storage node is automatically discharged to the extent that the switching state of the transistor component is redefined and hence the information stored in the semiconductor memory cell is lost.
Advantageously, the column structures are randomly distributed in the area above the channel region of the transistor component. Such a structure can be produced inexpensively independently of lithography.
One advantageous feature of the invention is that each of the column structures includes a plurality of semiconductor layer zones and insulating layer zones arranged alternately. This means that the charge stored in the bottommost semiconductor layer zone is held there even more effectively and consequently the storage time is extended.
Preferably, each column structure of the storage node is at least partly surrounded by the control gate electrode. This permits extremely effective punch-through of the potential on the control gate electrode through the entire column structure group, since the individual column structures are surrounded on all sides by the control gate electrode. Changing the gate potential shifts the energy level of the conduction band in the insulating layer zone(s) and in the adjoining semiconductor layer zones, which means that charge transfer can take place over the energy barrier(s) caused by the insulating layer zone(s) and possiblyxe2x80x94if the thickness of the insulating layer(s) is small enoughxe2x80x94even through it (xe2x80x9ctunnelingxe2x80x9d). As a result, the programming time is shortened considerably.
In a first preferred embodiment of the invention, the transistor component has a floating gate electrode, and the storage node is connected to the floating gate electrode either by an electrically conductive connection or capacitively. In both cases, as in the case of a conventional memory cell, the threshold voltage of the transistor component is shifted.
In a second preferred embodiment of the invention, the storage node itself forms the gate electrode of the transistor component. In this case, the floating gate electrode is dispensed with between the channel region of the transistor component and the storage node, i.e. the field produced by the charges stored in the column structures has a direct effect on the channel region of the transistor component. This semiconductor memory cell is of more compact design than in the case of the first embodiment.
Preferably, the column structures have a diameter of less than 50 nm, in particular of less than 30 nm.
By suitably reducing the lateral and axial dimensions of the semiconductor layer zones, the individual semiconductor layer zones can each have a very small capacitance. The effect achieved by this is that the potential barriers produced by the insulating layer zones are increased by the Coulomb blockade, i.e. the electrical conduction in the column structures can be produced by single-electron charge transfers.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a nonvolatile semiconductor memory cell, which includes steps of: forming transistor component having a source region, a channel region, and a drain region in a substrate; producing a channel insulating layer over the channel region; producing a layer sequence above the channel insulating layer; producing the layer sequence with at least two semiconductor layer zones and with an insulating layer configured between the two semiconductor layer zones; using a random mask to form a group of vertical column structures from the layer sequence; and forming a control electrode by depositing an electrically conductive material near the group of the column structures.
In accordance with an added mode of the invention, the step of forming the control electrode is performed by depositing the electrically conductive material between the individual column structures.
In accordance with an additional mode of the invention, the semiconductor layer zones are produced from silicon; and after forming the column structures, a lateral, self-limiting oxidation step is performed such that silicon column structures are produced which have reduced lateral dimensions with respect to the column structures that existed prior to the oxidation step.
In accordance with a concomitant mode of the invention, a layer, which includes an electrically conductive material, and a further insulating layer are deposited between the channel insulating layer and the layer sequence; and a structuring step is performed to form a floating gate electrode from the layer that includes the electrically conductive material such that the floating gate electrode is insulated on all sides.
A fundamental advantage of the inventive method is that the column structures are produced independently of lithography using a random mask, and also, only conventional process steps are required to produce the remainder of the nonvolatile semiconductor memory cell.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a nonvolatile semiconductor memory cell and method for fabricating same, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.